low voltage 1:5 differential lvds clock fanout buffer motorola semiconductor technical data product preview order number: MC100ES8014 rev 0, 05/2004 this document contains certain information on a new product. specifications and information herein are subject to change without notice . ? motorola, inc. 2004 low voltage 1:5 differential lvds the MC100ES8014 is a hstl differential clock fanout buffer. designed for the most demanding clock distribution systems, the MC100ES8014 supports various applications that require the dist ribution of precisely aligned differential clock signals. using sige technology and a fully differential architecture, the device offers very low skew outputs and s uperior digital signal characteristics. target applications for this clock driver are in high performance clock distribution in com puting, networki ng and telecomm unication systems. the MC100ES8014 is designed for low skew clock distribution systems and supports clock frequencies up to 400mhz. the device accepts two clock sources. the clk0 input accepts hstl compatible signals and clk1 accepts pecl compatible signals. the selected input signal is distributed to 5 identical, differential hstl compatible outputs. features ? 1:5 differential clock fanout buffer ? 50 ps maximum device skew ? sige technology ? supports dc to 400 mhz operation ? 1.5v hstl compatible differential clock outputs ? pecl and hstl compatible differential clock inputs ? 3.3v power supply for device core, 1.5v or 1.8v hstl output supply ? supports industrial temperature range ? standard 20 lead tssop package figure 1. 20-lead pinout (top view) and logic diagram v cco nc v ee clk1 clk1 en clk0 clk0 clk_sel v cc 20 19 18 17 16 15 14 13 12 11 10 1 2 3 45678 910 q0 q0 q1 q1 q2 q2 q3 q3 q4 q4 d q MC100ES8014 dt suffix 20 lead tssop package case 948e 1:5 differential hstl clock fanout driver ordering information device package MC100ES8014dt tssop-20 MC100ES8014dtr2 tssop-20 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc... data sheet MC100ES8014 idt? low voltage 1:5 differential lvds clock fanout buffer freescale timing solutions organization has been acquired by integrated device technology, inc MC100ES8014 1
MC100ES8014 motorola 2 timing solutions table 1. pin description pin function clk0, clk0 hstl data inputs clk1, clk1 pecl data inputs q[0:4], q[0:4] hstl data outputs clk_sel lvcmos active clock select input en lvcmos sync enable v cc positive supply of device core (3.3v) v cco positive power supply of the hstl outputs. al l vcco pins must be connected to the positive power supply (1.5v or 1.8v) for correct dc and ac operation. v ee negative supply nc no connect table 2. function table control default 0 1 clk_sel 0 clk0, clk0 (hstl) is the acti ve differential clock input clk1, clk1 (pecl) is the acti ve differential clock input en 0 q[0:4], q[0:4] are active. deassertion of en can be asynchronous to the reference clock without generation of output runt pulses. q[0:4] = l, q[0:4] = h (outputs disabled). assertion of en can be asynchronous to the reference clock without generation of output runt pulses. table 3. general specifications characteristics value internal input pulldown resistor tbd internal input pullup resistor tbd esd protection human body model machine model tbd ja thermal resistance (junction to ambient) 0 lfpm, 8 soic 500 lfpm, 8 soic tbd meets or exceeds jedec spec eia/jesd78 ic latchup test table 4. absolute maximum ratings 1 1. absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. exposure to these c onditions or conditions beyond those indicated may adv ersely affect device reliability. functi onal operation at absolute-maximum-rated co nditions is not implied. symbol parameter conditions rating unit v supply power supply voltage difference between v cc & v ee 3.9 v v in input voltage v cc ? v ee 3.6v v cc + 0.3 v ee ? 0.3 v v i out output current continuous surge 50 100 ma ma t a operating temperature range ?40 to +85 c t stg storage temperature range ?65 to +150 c freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc... MC100ES8014 low voltage 1:5 differential lvds clock fanout buffer netcom idt? low voltage 1:5 differential lvds clock fanout buffer freescale timing solutions organization has been acquired by integrated device technology, inc MC100ES8014 2
MC100ES8014 timing solutions 3 motorola table 5. dc characteristics (v cc = 3.3v5%; t j = 0c to 110c) 1 1. dc characteristics are design targets and pending characterization. symbol characteristic min typ max unit condition hstl differential input signals (clk0, clk0 ) v dif differential input voltage 2 2. v dif (dc) is the minimum differential hstl inpu t voltage swing required for device functionality. 0.2 v v x, in differential cross point voltage 3 3. v x (dc) is the crosspoint of the differential hstl input signal. f unctional operation is obtained when the crosspoint is within the v x (dc) range and the input swing lies within the v pp (dc) specification. 0.25 0.68 ? 0.9 v cc ? 1.3 v v ih input high voltage v x + 0.1 v v il input low voltage v x ? 0.1 v i in input current 150 ma v in = v x 0.1v pecl differential input signals (clk1, clk1 ) v pp differential input voltage 4 4. v pp (dc) is the minimum differential input voltage swing required to maintain device functionality. 0.15 1.0 v differential operation v cmr differential cross point voltage 5 5. v cmr (dc) is the crosspoint of the differential input signal. functi onal operation is obtained when the crosspoint is within the v cmr (dc) range and the input swing lies within the v pp (dc) specification. 1.0 v cc ? 0.6 v differential operation v ih input high voltage v cc ? 1.165 v cc ? 0.880 v v il input low voltage v cc ? 1.810 v cc ? 1.475 v i in input current 150 ma v in = v ih or v in lvcmos control inputs en , clk_sel v il input low voltage 0.8 v v ih input high voltage 2.0 v i in input current 150 ma v in = v ih or v in hstl clock outputs (q[0:4], q[0:4] ) v x, out output differential crosspoint 0.68 0.75 0.9 v v oh output high voltage 1 v v ol ouput low voltage 0.4 v supply current i cc maximum quiescent supply current without output termination current tbd tbd ma v cc pin (core) i cco maximum quiescent supply current, outputs terminated 50 ? to v tt tbd tbd ma v cco pin (outputs) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc... MC100ES8014 low voltage 1:5 differential lvds clock fanout buffer netcom idt? low voltage 1:5 differential lvds clock fanout buffer freescale timing solutions organization has been acquired by integrated device technology, inc MC100ES8014 3
MC100ES8014 motorola 4 timing solutions table 6. ac characteristics (v cc = 3.3v5%; t j = 0c to 110c) 1 2 1. ac characteristics are design ta rgets and pending characterization. 2. ac characteristics apply for parallel output termination of 50 ? to v tt. symbol characteristic min typ max unit condition hstl/lvds differential input signals (clk0, clk0 ) v dif differential input voltage (peak-to-peak) 3 3. v dif (ac) is the minimum differential hstl input voltage swing requir ed to maintain ac characteristics including tpd and device-to- device skew. 0.4 v v x, in differential cross point voltage 4 4. v x (ac) is the crosspoint of the differential hstl input signal . functional operation is obtained w hen the crosspoint is within t he v x (ac) range and the input swing lies within the v dif (ac) specification. violation of v x (ac) or v dif (ac) impacts the device propagation delay, device and part-to-part skew. 0.68 0.9 v f clk input frequency 0 ? 400 tbd mhz differential t pd propagation delay tbd ps differential pecl differential input signals (clk1, clk1 ) v pp differential input voltage (peak-to-peak) 5 5. v pp (ac) is the minimum differential pecl input voltage swing requi red to maintain ac characteri stics including tpd and device-to- device skew. 0.2 1.0 v v cmr differential cross point voltage 6 6. v cmr (ac) is the crosspoint of the differen tial pecl input signal. normal ac operation is obtained when the crosspoint is within th e v cmr (ac) range and the input swing lies within the v pp (ac) specification. violation of v cmr (ac) or v pp (ac) impacts the device propagation delay, device and part-to-part skew. 1v cc ? 0.6 v f clk input frequency 0 ? 400 mhz differential t pd propagation delay tbd ps differential hstl clock outputs (q[0:4], q[0:4] ) v x, out output differential crosspoint 0.68 0.75 0.9 v v oh output high voltage 1 v v ol ouput low voltage 0.5 v v o(p-p) differential output voltage (peak-to-peak) 0.5 v t sk(o) output-to-output skew 50 ps differential t sk(pp) output-to-output skew (part-to-part) tbd ps differential t jit(cc) output cycle-to-cycle jitter tbd dc o output duty cycle tbd 50 tbd % dc fref = 50% t r / t f output rise/fall times 0.05 tbd ns 20% to 80% t pdl output disable time 7 7. propagation delay en deassertion to differential output disabled (differential low: true output low, complementary output high). 2.5*t +t pd 3.5*t +t pd ns t = clk period t pld output enable time 8 8. propagation delay en assertion to output enabled (active). 3*t +t pd 4*t +t pd ns t = clk period freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc... MC100ES8014 low voltage 1:5 differential lvds clock fanout buffer netcom idt? low voltage 1:5 differential lvds clock fanout buffer freescale timing solutions organization has been acquired by integrated device technology, inc MC100ES8014 4
MC100ES8014 timing solutions 5 motorola figure 2. MC100ES8014 ac test reference clkx t pdl (en to qx[]) 50% t pld (en to qx[]) clkx en qx[] qx[] outputs disabled figure 3. MC100ES8014 ac test reference differential pulse generator z = 50? r t = 50 ? z o = 50 ? dut MC100ES8014 v tt =gnd r t = 50 ? z o = 50 ? v tt =gnd figure 4. MC100ES8014 ac reference measurement wavefo rm (hstl input) clk0,1 t pd (clk0,1 to q[0?4]) v x =0.75v v dif =1.0v clk0,1 q[0?4] q[0?4] t pd (clk0,1 to q[0?4]) v cmr =v cc ?1.3v v pp =0.8v clk0,1 clk0,1 q[0?4] q[0?4] figure 5. MC100ES8014 ac reference measurement wavef orm (pecl input) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc... MC100ES8014 low voltage 1:5 differential lvds clock fanout buffer netcom idt? low voltage 1:5 differential lvds clock fanout buffer freescale timing solutions organization has been acquired by integrated device technology, inc MC100ES8014 5
idt? low voltage 1:5 differential lvds clock fanout buffer freescale timing solutions organization has been acquired by integrated device technology, inc MC100ES8014 6 MC100ES8014 low voltage 1:5 differential lvds clock fanout buffer netcom MC100ES8014 motorola 6 timing solutions package dimensions dt suffix 20 lead tssop package case 948e-02 issue a 10 11 20 pin 1 ident a b -v- -u- s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t s u 0.15 (0.006) t c d g h seating plane -w- detail e n n m f 0.25 (0.010) detail e section n-n k k1 jj1 0.100 (0.004) ?t? pin 1 ident a b -v- -u- s u m 0.10 (0.004) v t 20x ref k l l/2 2x s u 0.15 (0.006) t s u 0.15 (0.006) t case 948e 02 inches millimeters 0.65 bsc 0.026 bsc 6.40 bsc 0.252 bsc dim a b c d f g h j j1 k k1 l m max 6.60 4.50 1.20 0.15 0.75 0.37 0.20 0.16 0.30 0.25 8? max 0.260 0.177 0.047 0.006 0.030 0.015 0.008 0.006 0.012 0.010 8? min 4.30 0.05 0.50 0.27 0.09 0.09 0.19 0.19 0? 6.40 --- min 0.169 0.002 0.020 0.011 0.004 0.004 0.007 0.007 0? 0.252 --- notes: 1. 2. 3. 4. 5. 6. 7. dimensioning and tolerancing per ansi y14.5m, 1982. controlling dimension: millimeter. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. terminal numbers are shown for reference only. dimension a and be are to be determined at datum plane -w-. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC100ES8014 low voltage 1:5 differential lvds clock fanout buffer netcom mpc92459 900 mhz low voltage lvds clock synthesizer netcom ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 innovate with idt and accelerate your future networks. contact: www.idt.com part numbers insert product name and document title netcom
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